HDL API & Gate Design Reference

This document details API, schematic design, and HDL implementation for the nand2tetris course (based on "The Elements of Computing Systems"). All HDL implementations have been tested through the Hardware Simulator. (this project is hosted on Github)

Note: schematics, truth tables, and HDL are only included where appropriate.

Not16

Inputs in[16]
Outputs out[16]
SOP !in[i]
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And16

Inputs a[16], b[16]
Outputs out[16]
SOP ab
▲

Or8Way

Inputs in[8]
Outputs out
SOP in[0]+in[1]+..+in[7]
▲

Or16

Inputs a[16], b[16]
Outputs out[16]
SOP a[i]+b[i]
▲

Mux

Inputs a, b, sel
Outputs out
SOP s̄a+s̄b
sel out
0 a
0 b
▲

Mux16

Inputs a[16], b[16], sel
Outputs out[16]
▲

Mux4Way

Inputs a, b, c, d, sel[2]
Outputs out
sel[0] sel[1] out
0 0 a
0 1 b
1 0 c
1 1 d
▲

Mux4Way16

Inputs a[16], b[16], sel[2]
Outputs out[16]
▲

Mux8Way

Inputs a, b, c, d, e, f, g, h, sel[3]
Outputs out
sel[0] sel[1] sel[2] out
0 0 0 a
0 1 0 b
1 0 0 c
1 1 0 d
0 0 1 e
0 1 1 f
1 0 1 g
1 1 1 h
▲

Mux8Way16

Inputs a[16], b[16], c[16], d[16], e[16], f[16], g[16], h[16], sel[3]
Outputs out
▲

DMux

Inputs in, sel
Outputs a, b
SOP a=xs̄, b=xs
sel a b
0 in 0
1 0 in
▲

DMux4Way

Inputs in, sel[2]
Outputs a, b, c, d
sel[0] sel[1] a b c d
0 0 in 0 0 0
0 1 0 in 0 0
1 0 0 0 in 0
1 1 0 0 0 in
▲

DMux8Way

Inputs in, sel[3]
Outputs a, b, c, d, e, f, g, h, out
sel[0] sel[1] sel[2] out
0 0 0 a
0 1 0 b
1 0 0 c
1 1 0 d
0 0 1 e
0 1 1 f
1 0 1 g
1 1 1 h
Note: this table is shortened.
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Bit

Inputs in, load
Outputs out
▲

Register

Inputs in[16], load
Outputs out[16]
▲

PC

Inputs in[16], load, inc, reset
Outputs out[16]
▲

RAM8

Inputs in[16], load, address[3]
Outputs out[16]
▲

RAM64

Inputs in[16], load, address[6]
Outputs out[16]
▲

RAM512

Inputs in[16], load, address[9]
Outputs out[16]
▲

RAM4K

Inputs in[16], load, address[9]
Outputs out[16]
▲

RAM16K

Inputs in[16], load, address[14]
Outputs out[16]
▲